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SUNNYVALE, Calif.--(BUSINESS WIRE)--June 4, 2001-- Synplicity Inc. (Nasdaq: SYNP), a leading supplier of software for the design and verification of semiconductors, today introduced the industry's first timing-driven ASIC synthesis product optimized to improve productivity for the majority of ASIC designers. Leveraging the proprietary synthesis algorithms that have made Synplicity's FPGA synthesis and ASIC verification products successful, Synplicity's new Synplify ASIC(TM) software is able to provide designers with a fast, easy-to-use and powerful ASIC synthesis solution. For designers who need the fastest time to market, the software boasts runtimes up to 15 times faster than traditional synthesis products. Further improving productivity, the Synplify ASIC software offers a unique ``top-down'' design methodology that enables designers to perform timing-driven synthesis on up to two-million-gate designs in a single operation, supporting matching hierarchy and constraints in synthesis and place and route steps.

``In the FPGA synthesis market, we believe we have provided more than 1,400 design organizations with a fast and easy-to-use solution that obtains high quality of results,'' said Ken McElvain, co-founder and chief technical officer at Synplicity. ``In response to frequent requests from our customers, more than 30 percent of whom design both FPGAs and ASICs, we are now offering an ASIC synthesis solution which we expect will provide the same productivity benefits they have come to expect from Synplicity.''

According to research from Collett International, the majority of today's ASIC designs is between 500,000 and one million gates and is implemented in 0.18 micron or higher process geometries. Along with its customers and ASIC Synthesis Advisory Panel members, Synplicity identified several barriers these designers face in achieving productivity in ASIC synthesis, including: the need for extensive scripting, long runtimes which limit the number of iterations per day; mismatches between synthesis and physical design hierarchies which impede timing closure; unpredictable behavior of tools; and long training time needed to begin using a synthesis tool. With the Synplify ASIC product, Synplicity seeks to remove these barriers and to deliver an order-of-magnitude improvement in designer productivity.

Dave Roth, director of ASIC development at Allegro Networks, a developer of router technology for enhanced network capability, said, ``We were skeptical that a new synthesis tool could generate great results in a fraction of the time; the Synplify ASIC software has proven us wrong!''

The Synplify ASIC software is driven by Synplicity's core synthesis technology, the proprietary Behavior Extracting Synthesis Technology® (B.E.S.T.(TM)) algorithms and Synthesis Constraint Optimization Environment® (SCOPE®). Using this technology, the Synplify ASIC software enables the rapid synthesis of an ASIC design -- up to 15 times faster than traditional synthesis products -- with high quality of results. The software features a fast and accurate incremental timing engine for timing-critical designs and offers designers the flexibility to use either a command line interface for TCL scripting or an intuitive graphical user interface that simplifies the design process. The software also features Synplicity's popular HDL Analyst® RTL graphical analysis tool to ease the debugging process.

Vince Hopkin, Vice President, Conversion ASIC Business Unit, AMI Semiconductor, said, ``AMI Semiconductor has made Synplicity's Synplify ASIC product the recommended FPGA-to-ASIC synthesis tool for our customers because it directly addresses our customers' most compelling design and time-to-market needs by generating excellent results in the shortest time possible.''

With the introduction of the Synplify ASIC product, Synplicity offers a path from a single RTL design file to an FPGA, multiple FPGAs or an ASIC. In addition, many ASIC designers today use programmable logic to test all or part of their designs before committing the design to ASIC production. For these customers, many of whom currently use Synplicity® technology, the Synplify ASIC product can quickly re-target single-FPGA Synplify® and multi-FPGA Certify(TM) project files to an ASIC vendor implementation with a few mouse-clicks. Combined with the fast runtimes of the Synplify ASIC software, this capability creates a fast path for conversion of FPGA designs into ASIC implementations.

The Synplify ASIC Software: Users Become Proficient in a Day

Leveraging its core synthesis algorithms, Synplicity has helped to reduce or eliminate the need for the complex scripts and commands normally associated with synthesis products, enabling designers to focus on improving their designs rather than on manipulating their synthesis tool. In automating the synthesis process, Synplicity has created an easy-to-learn and easy-to-use ASIC synthesis solution. As a result, Synplicity believes it is possible for designers to become proficient users of the software in a single day, compared to weeks or months for current synthesis products.

By delivering a product that is easy to learn and easy to use, Synplicity also helps eliminate many of the resource management issues engineering managers must consider. According to Collett International, an average design team has more than nine people with varying degrees of engineering experience involved in the synthesis process. Considering an individual designer's experience with a specific tool when assigning tasks can quickly become a management problem and can lead to a lack of qualified people able to do specific tasks.

Top-Down Methodology

The Synplify ASIC solution provides designers with a top-down methodology, enabling users to synthesize an entire design of more than two million gates, often in one pass. After synthesizing the design from the RTL code, the tool provides a gate-level netlist that is optimized for place and route. By incorporating this top-down methodology, a designer avoids having to break up the design into separate blocks and manually synthesize each block, reducing design time and engineering resources.

Zvi Or-Bach, President & CEO, eASIC Corporation, said, ``We have been very impressed with the results we've achieved using Synplify ASIC, especially its ability to quickly optimize performance for our eASICore architecture. We enjoy the advantages provided by its software tools and look forward to a continued relationship with Synplicity.''

Automation of Tedious Design Tasks

Further improving productivity and speeding design time, Synplicity automated many of the time-consuming and tedious tasks traditionally required by synthesis products, including:

• Time budgeting -- automatic optimization of timing across the design hierarchy without manual scripting and time budgeting
• Integrated module generation for high-performance and area-efficient implementations of arithmetic and datapath functions
• HDL syntax and synthesis checks for both Verilog and VHDL

HDL Analyst Debug Functionality

To help identify critical paths, the Synplify ASIC software features Synplicity's HDL Analyst RTL graphical analysis and debugging tool. Using ASIC vendor-specific symbols, this feature provides users with an instant graphical view of both high-level block diagrams and gate-level schematics linking back to the HDL source code, offering clear visualization of design data.

Pricing and Availability

The Synplify ASIC software is available now for Windows NT 4.0, Windows 2000 and Solaris 2.7 operating systems. A perpetual license of the Synplify ASIC software costs $115,000. A one-year time-based license of the Synplify ASIC software costs $69,000. Through 2001, existing Synplicity customers can purchase the Synplify ASIC software for half the list price.

About Synplicity

Synplicity, Inc. (Nasdaq: SYNP) is a leading provider of software products that enable the rapid and effective design and verification of semiconductors used in next-generation networking and communications hardware and other electronic devices. The company leverages its innovative logic synthesis, physical synthesis and verification software solutions to improve performance and shorten development time for complex programmable logic devices, application specific integrated circuits (ASICs) and system-on-chip (SoC) integrated circuits. Synplicity's fast, easy-to-use products offer high quality of results, support industry-standard design languages (VHDL and Verilog) and run on popular platforms. As of the end of March 2001, Synplicity employed over 230 people in its 16 facilities worldwide. Synplicity is headquartered in Sunnyvale, Calif.

The specific features, functionality and release timing of any new products or new versions of current products remain at the sole discretion of Synplicity, Inc., and Synplicity does not make any warranty as to when or if specific features, functionality or releases may occur.

Forward-looking Statement

This press release contains forward-looking statements. These statements relate to future events and involve known and unknown risks, uncertainties and other factors that may cause Synplicity's actual product performance or achievements to differ materially from those expressed or implied by the forward-looking statements. In some cases, you will be able to identify forward-looking statements by terminology such as ``anticipates,'' ``intends,'' ``may,'' ``will,'' ``expects,'' ``potential,'' ``continue'' or the negative of these terms or other comparable terminology. Forward-looking statements are only predictions and the actual events or results may differ materially, particularly with respect to the continued acceptance of Synplicity's existing products and the successful introduction and widespread market acceptance of Synplicity's new products, especially Synplify ASIC. For additional information and considerations regarding the risks faced by Synplicity, see its Registration Statement on Form S-1 and Form 10-K for the fiscal year ended December 31, 2000, as well as periodic reports on Forms 10-Q as filed with the Securities and Exchange Commission. Although Synplicity believes that the expectations reflected in the forward-looking statements are reasonable, Synplicity cannot guarantee future results, levels of activity, performance or achievements. In addition, neither Synplicity nor any other person assumes responsibility for the accuracy and completeness of these forward-looking statements. Synplicity disclaims any obligation to update information contained in any forward-looking statement.

Synplicity, Synplify, HDL Analyst, Behavior Extracting Synthesis Technology, Synthesis Constraints Optimization Environment and SCOPE are registered trademarks of Synplicity, Inc. Synplify ASIC, Certify, and B.E.S.T. are trademarks of Synplicity, Inc. All other names mentioned herein are the trademarks or registered trademarks of their owners.

     Synplicity, Inc.
     John Gallagher, 408/215-6000
     johng@synplicity.com
           or
     Tsantes/Porter Novelli
     Steve Gabriel, 408/369-1500 x27
     steve@tsantes.com